`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/05 18:33:29
// Design Name: 
// Module Name: registers
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module registers(
    clk,reset_n,op_rd,addr_ir,rd,rs1,rs2,data,data_mem,data1,data2
    );
    
    input clk;
    input reset_n;
    input [1:0] op_rd;
    input [31:0] addr_ir;
    input [4:0] rd;
    input [4:0] rs1;
    input [4:0] rs2;
    input [31:0] data;
    input [31:0] data_mem;
    output reg [31:0] data1;
    output reg [31:0] data2;

    reg [31:0] data3;

    reg [31:0] registers [31:0];

    parameter data_d=0,data_r=1,data_m=2;
    always @(*) begin
        if(~reset_n) begin
            registers[0] = 32'b0;
            registers[1] = 32'b11;
            // registers[2] = 32'b11;
            // registers[3] = 32'b1011;
            registers[4] = 32'b100;
            registers[5] = 32'b100;
            // registers[6] = 32'b1011;
            //registers[7] = 32'b0;
            registers[8] = 32'b0;
        end
        else begin
            data1 = registers[rs1];
            data2 = registers[rs2];
        end
    end
    
    // always @(negedge clk) begin
    //     data1 <= registers[rs1];
    //     data2 <= registers[rs2];
    // end

    always @(negedge clk) begin
        case (op_rd)
            data_d : registers[rd] <= data;
            data_r : registers[rd] <= addr_ir;
            data_m : registers[rd] <= data_mem; 
        endcase
    end

endmodule
